In modern SRAMbased Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which\ncan realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this\narea overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases.\nIn this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory\n(SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits.We then propose\nseveral methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent\nfunctions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean\nmatching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two\nLUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes\n(4ââ?¬â??7), while varying the cluster sizes (4ââ?¬â??16). Experimental results onMCNC benchmark circuits set show an overall area reduction\nof âË?¼7% while maintaining the same critical path delay.
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